NC-Raleigh, Minimum Qualifications: 1-5 years of experience in the following: – Design and/or verification experience on a CPU (especially RISC). – Knowledge of CPU architecture and use of assembly language (especially RISC). – Ability to debug Verilog RTL in a System Verilog/UVM environment – Prior use of industry standard simulators and waveform debuggers – Perl – Competent use of Unix/Linux command line an
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